Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!csd4.milw.wisc.edu!bionet!ames!oliveb!tymix!cirrusl!sunkist!grenley
From: grenley@sunkist.UUCP (George Grenley)
Newsgroups: comp.arch
Subject: Silicon Innovation - was Re: Purchasing Agents and Pontiffs
Message-ID: <744@cirrusl.UUCP>
Date: 18 May 89 19:24:26 GMT
References: <25395@ames.arc.nasa.gov> <28200315@mcdurb> <19913@obiwan.mips.COM> <40106@bbn.COM>
Sender: news@cirrusl.UUCP
Reply-To: grenley@sunkist (George Grenley)
Organization: CIRRUS LOGIC Inc.
Lines: 22

In article <40106@bbn.COM> slackey@BBN.COM (Stan Lackey) writes:
>I remember trying to convince reps from semi houses that they should
>make an edge-triggered SRAM; they could do away with the
>address-line-change detector circuits, and have a dandy edge to start
>the timing chain, and we would have a faster RAM with a built-in
>address register.  The response?  "Shut up, you're a system designer.
>You don't know anything about RAM's."  We even could never convince them
>that you don't need a cycle time equal to access time!

I worked at Mostek in the earlt eighties; at that time they made a line 
of edge triggered (CS*) SRAMs and ROMs - state of the art in speed
and density, too (for the time).

Boy, did you system designers beat us up on that!!!

The market SCREAMED for access time = cycle time, no clocking required,
full ripple through operation.  I recall practically being thrown out
of customers for even suggesting they provide a clock.

Guess you weren't one of 'em, though, Stan ;-)

It's worth noting, BTW - Mostek doesn't make much of anything anymore.