Path: utzoo!attcan!utgpu!jarvis.csri.toronto.edu!mailrus!ames!lll-winken!vette!brooks
From: brooks@vette.llnl.gov (Eugene Brooks)
Newsgroups: comp.arch
Subject: Re: Simple query about Cray-2 architecture
Message-ID: <25538@lll-winken.LLNL.GOV>
Date: 19 May 89 15:37:16 GMT
References: <2556@ast.cs.vu.nl>
Sender: usenet@lll-winken.LLNL.GOV
Reply-To: brooks@maddog.llnl.gov (Eugene Brooks)
Organization: Lawrence Livermore National Laboratory
Lines: 23

In article <2556@ast.cs.vu.nl> ast@cs.vu.nl (Andy Tanenbaum) writes:
>
>I have a simple question about the Cray-2.  Does it have basically the
>same ARCHITECTURE as the Cray-1 (in terms of number of registers,
>instruction format, instruction set etc.?  I'd appreciate e-mail from
>anyone in the know as I haven't been able to find too much about it in
>the literature (references welcome).  
The architecture is pretty close, but not close enough for full instruction
set compibility.  The address registers are a full 32 bits, instead of 24.
The number of address, data, and vector registers are the same.  The length
of the vector registers is the same.  There are 64 B and 64 T registers on
the Cray-1, which are replaced by a 16K word local memory on the Cray-2.  The
implementation technology of the Cray-2 limits it to an instruction issue every
other clock, you get one per clock on the Cray-1.  There is no chaining on the
Cray-2, there is chaining on the Cray-1 if you hit the timing right.  Both
machines have one port to memory, compared to three on the XMP series.  The
XMP can run Cray-1 binaries, the Cray-2 can not.  The Cray-2 and later XMP
models support compress and gather/scatter, the Cray-1 does not.

No doubt I made an error somewhere, and someone will flame for for it!


brooks@maddog.llnl.gov, brooks@maddog.uucp