Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!tut.cis.ohio-state.edu!cs.utexas.edu!uunet!mcvax!hp4nl!botter!star.cs.vu.nl!ast From: ast@cs.vu.nl (Andy Tanenbaum) Newsgroups: comp.os.minix Subject: Re: What's the magic about using DMA?? Message-ID: <2535@ast.cs.vu.nl> Date: 17 May 89 07:03:40 GMT References: Reply-To: ast@cs.vu.nl (Andy Tanenbaum) Distribution: comp.os.minix Organization: VU Informatica, Amsterdam Lines: 19 In article cline@sun.soe.clarkson.edu (Marshall Cline) writes: >(1) I recently read in the Minix textbook (Prentice Hall) about a DMA >caveat that AST had discovered. It had something to do with wrapping >around 64K barriers as I recall. The PC has a 16-bit DMA chip. To generate 20-bit PC bus address, it has a 4-bit register for the high-order bits. When the 16-bit counter overflows, it just wraps around, but there is no carry to the 4-bit register. Thus if you transfer 100 bytes to address 65530, the first 6 bytes go fine. At that point the 4-bit register is 0000 and the 16-bit register is all 1's. When the 16-bit counter is incremented by the DMA chip, it goes to 0. The 4-bit counter stays 0. The next 96 bytes of DMA overwrite absolute addresses 0-95 (the interrupt vectors). At the next interrupt, probably from the clock, the hardware vectors to a totally random address. This is why I always teach my students that no hardware designer should be allowed to produce any piece of hardware until 3 software guys have signed off for it. Andy Tanenbaum (ast@cs.vu.nl)