Path: utzoo!attcan!utgpu!jarvis.csri.toronto.edu!mailrus!ukma!tut.cis.ohio-state.edu!rutgers!sunybcs!bowen
From: bowen@cs.Buffalo.EDU (Devon E Bowen)
Newsgroups: comp.sys.cbm
Subject: 6551 interfacing
Message-ID: <5944@cs.Buffalo.EDU>
Date: 18 May 89 18:36:29 GMT
Sender: bowen@cs.Buffalo.EDU
Reply-To: bowen@cs.Buffalo.EDU (Devon E Bowen)
Organization: SUNY/Buffalo Computer Science
Lines: 26

I'm currently working on a board for the expansion bus that will give the
64 a 6551 UART for much higher baud rates. I finished the wiring last night,
plugged it in and it almost works. I've got the chip set up so it takes
over the I/O expansion area number 1 from 6E00 to 6EFF by running the
chip select directly to the IO1 pin on the bus. The problem I'm having is
that sometimes it takes more than one write to actually get the data to
the chip and sometimes reading multiple times from a chip register that
should be constant gives different results.

It was suggested to me that I might have some contention between chips
which is very possible considering the area I'm working in can be used for
I/O, RAM or character ROM. But the default memory configuration has I/O
in this area, and I didn't touch the configuration, so I assume it should
work ok. The one thought I had was that maybe I have to do something
with either the GAME line or the EXROM line. These lines aren't described
very well in the book and on the schematics the logic gets lost in the
PLA. Anyone know if I need to tug on one of these?

Any other suggests would be appreciated, too. Maybe I should just stick to
software...  8-)


Devon Bowen (KA2NRC)		FAX:	   (716) 636-3464
University at Buffalo		BITNET:    bowen@sunybcs.BITNET
				Internet:  bowen@cs.Buffalo.EDU
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