Path: utzoo!attcan!utgpu!jarvis.csri.toronto.edu!mailrus!ames!ncar!boulder!sunybcs!bowen
From: bowen@cs.Buffalo.EDU (Devon E Bowen)
Newsgroups: comp.sys.cbm
Subject: Re: 6551 interfacing
Message-ID: <5970@cs.Buffalo.EDU>
Date: 19 May 89 19:22:12 GMT
References: <5944@cs.Buffalo.EDU> <6925@cbmvax.UUCP>
Reply-To: bowen@sunybcs.UUCP (Devon E Bowen)
Organization: SUNY/Buffalo Computer Science
Lines: 15

In article <6925@cbmvax.UUCP> daveh@cbmvax.UUCP (Dave Haynie) writes:
>I admit it's been awhile, but aren't the I/O spaces at DExx and DFxx?

Yep. That was a typo.

>I suspect that you're having setup time problems.  Basically, you can't
>just hook a 6526 up to the expansion bus and expect it to work OK.  The
>chip select and addresses must be valid at least 90ns before the PHI2
>clock goes high.

That could be it. I'm still pretty new to all this hardware stuff, and
I'm still overlooking things like timing. Live and learn. Thanks for the
suggestion. I'll give it a try this weekend.

Devon