Path: utzoo!attcan!uunet!mcvax!ukc!stl!idec!camcon!igp
From: igp@camcon.co.uk (Ian Phillipps)
Newsgroups: comp.sys.ibm.pc
Subject: Re^2: Optimizers and RISC
Message-ID: <2911@titan.camcon.co.uk>
Date: 18 May 89 13:42:35 GMT
References: <7632@phoenix.Princeton.EDU> <256@jwt.UUCP> <7697@phoenix.Princeton.EDU> <268@tree.UUCP> <13595@ncoast.ORG> <369@utgard.UUCP> <3181@looking.UUCP> <13628@ncoast.ORG>
Organization: Cambridge Consultants Ltd., Cambridge, UK
Lines: 17

allbery@ncoast.ORG (Brandon S. Allbery) writes:

>As quoted from <3181@looking.UUCP> by brad@looking.UUCP (Brad Templeton):

>Optimization under RISC consists primarily of (1) recognizing that some
>loops will run faster when "unwound" into linear code and (2) optimizing the
>use of registers.

And, maybe more important, re-ordering instructions so that the processor
doesn't stall if a register value is still in the pipeline, and that the
delay cycle after jumps is used constructively. These don't apply to any
CISC processors I know of [ok. maybe mainframes, but no-one's given me one
to play with].
-- 
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