Xref: utzoo comp.arch:9674 comp.sys.intel:804
Newsgroups: comp.arch,comp.sys.intel
Path: utzoo!henry
From: henry@utzoo.uucp (Henry Spencer)
Subject: Re: Need information about 386 performance
Message-ID: <1989May11.210457.2068@utzoo.uucp>
Organization: U of Toronto Zoology
References: <390@unixprt.UUCP>
Date: Thu, 11 May 89 21:04:57 GMT

In article <390@unixprt.UUCP> paf@unixprt.UUCP (Paul Fronberg) writes:
>I am doing analysis of the i386 for use as in a controller and am having
>problems relating calculated timings with measured timings. Does anyone
>know about any documentation, ap-notes, or such that might be available
>from Intel that describes the inner workings of the i386, especially how
>the various phases of the pipeline interacts.

Do remember that any such documentation has a good chance of being specific
to a particular release of the chip, which may not be the one you've got
(or the one that will be available when your design goes into production).
This is the sort of thing that manufacturers will often fiddle with as
time goes by, especially to fix bugs.

>The measured time and calculated time are very different for several
>test code fragments...
>... I suspect I am seeing collisions between instruction
>prefetch and instruction memory accesses. Things seem to be very complicated...

Things are sufficiently complicated that what you're trying to do may well
be impossible in a practical sense.  It's very hard to compute accurate
and precise timings for modern CISC machines, and even RISC designs make
it only somewhat easier.
-- 
Mars in 1980s:  USSR, 2 tries, |     Henry Spencer at U of Toronto Zoology
2 failures; USA, 0 tries.      | uunet!attcan!utzoo!henry henry@zoo.toronto.edu