Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!ncar!ames!ucsd!sdcsvax!celece!markley
From: markley@celece.ucsd.edu (Mike Markley)
Newsgroups: comp.windows.x
Subject: Re: Graph Layouts?
Message-ID: <6428@sdcsvax.UCSD.Edu>
Date: 17 May 89 19:26:19 GMT
References: <3930006@hpclada.HP.COM>
Sender: nobody@sdcsvax.UCSD.Edu
Reply-To: markley@celece.UUCP (Mike Markley)
Organization: UCSD Office of Academic Computing
Lines: 16

In article <3930006@hpclada.HP.COM> sridhar@hpclada.HP.COM (Sridhar Ramakrishnan) writes:
>I am interested in looking into the problem of good graph-layout algorithms.
>Some of the constraints could be:
>	a) minimum area occupied by the N points,
>	b) minimum path length,
>	c) minimum overlap of arcs between nodes,
>	d) maximum length of an arc, etc
>
me too!
Although I have access to a variety of IC layout and compaction
algorithms I would be interested in any other approaches.

Mike Markley
University of California, San Diego
markley@celece.ucsd.edu
markley@kubrick.ucsd.edu