Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!tut.cis.ohio-state.edu!ucbvax!hplabs!hp-pcd!hpvcfs1!johne
From: johne@hpvcfs1.HP.COM (John Eaton)
Newsgroups: sci.electronics
Subject: Re: SRAM Battery backup
Message-ID: <1430003@hpvcfs1.HP.COM>
Date: 15 May 89 19:21:43 GMT
References: <657@serene.UUCP>
Organization: Hewlett Packard, Vancouver, WA
Lines: 23

<<<< 
< Alright, enough of the description...  I would like to battery back the
< RAM.  Its a 6264LP-15.  I have the appropriate diodes set up so the
< battery doesn't try to run the rest of the circuit, and so that it does
< not get charged by the power supply.
----------
Thats the first step. You must also ensure that the CS2 is driven
DEEPLY into its inactive state during power down. By deeply I mean to
within 200 mv of the rails because the static current at Vih or Vil is
about 500X the current when driven to the rails. It is extremely important 
that you guarentee that the ram is not accessed during powerdown because
even a read will cause its current to jump by a factor of about 30,000.

When doing a battery backed design you must ensure that no signal from the
battery section is allowed to drive ANY unpowered device pin high. If you
do then the signal will attempt to power its VDD line through the input
protection diodes and you will see high current. If its a CMOS design then
the circuit may even still run. Power down the circuit and check the voltage
at the VDD pins of the chips that should be off. If you see 1 to 2 volts then
you have problems.

John Eaton
!hpvcfs1!johne