Path: utzoo!attcan!utgpu!jarvis.csri.toronto.edu!rutgers!sun-barr!cs.utexas.edu!uunet!ncrlnk!ncr-sd!serene!pnet12!gbell
From: gbell@pnet12.cts.com (Greg Bell)
Newsgroups: sci.electronics
Subject: Re: SRAM Battery backup
Message-ID: <662@serene.UUCP>
Date: 16 May 89 08:16:05 GMT
Sender: root@serene.UUCP
Organization: People-Net [pnet12], Del Mar, CA
Lines: 27

johne@hpvcfs1.HP.COM (John Eaton) writes:
><<<< 
>< Alright, enough of the description...  I would like to battery back the
>< RAM.  Its a 6264LP-15.  I have the appropriate diodes set up so the
>< battery doesn't try to run the rest of the circuit, and so that it does
>< not get charged by the power supply.
>----------
>Thats the first step. You must also ensure that the CS2 is driven
>DEEPLY into its inactive state during power down. By deeply I mean to
>within 200 mv of the rails because the static current at Vih or Vil is
>about 500X the current when driven to the rails. It is extremely important 
>that you guarentee that the ram is not accessed during powerdown because
>even a read will cause its current to jump by a factor of about 30,000.
>

Really?  A read will cause problems?  In other words, I need to jump to a
location in the monitor EPROM before powering down (there's no way to get the 
8031 to just "HALT".  Maybe driving RESET high and holding it would do)?  

Would the Maxim/Dallas Semi monitor chips pull the CS2 inactive soon enough so
that the circuit could be doing anything at powerdown without trouble?  After
all, isn't that the purpose of the chip?

    Greg Bell_________________________________________________________
      Hardware hacker          |
      Electronics hobbyist     | UUCP:  uunet!serene!pnet12!gbell
      EE major at UC San Diego |