Path: utzoo!attcan!utgpu!jarvis.csri.toronto.edu!rutgers!apple!versatc!leadsv!practic!vlsisj!davidc
From: davidc@vlsisj.VLSI.COM (David Chapman)
Newsgroups: sci.electronics
Subject: Re: SRAM Battery backup
Message-ID: <15227@vlsisj.VLSI.COM>
Date: 16 May 89 02:44:27 GMT
References: <657@serene.UUCP>
Reply-To: davidc@vlsisj.UUCP (David Chapman)
Organization: VLSI Technology Inc., San Jose, CA
Lines: 43

In article <657@serene.UUCP> gbell@pnet12.cts.com (Greg Bell) writes:
>How do I get the circuit to power down in an orderly fashion? ...
> 
>Is this RAM corruption due to a pulse on the WE/ (write enable) line? ... 
> 
>I've tried having the setup jump to an EPROM address so the RAM is quiet
>at power down, and I still have the problem.  Also, I've tried buffering
>the write line so that it can be pulled up when the power to the rest of
>the circuit goes down.  Its hard to tell what's making a difference since
>I can't tell what, if any, locations get corrupted at any one time.
> 
You really don't want to have anything running during the power-down
period.  If you can feed the "power down pending" signal to the non-
maskable interrupt line of the processor, and have it HALT, that might
reduce the incidence of the problem.  If you don't have advance notice
of power failure, then you need a power-fail-detection circuit and you
might as well buy the special chips.

You say that you pulled up the WE line during power-down.  Was the IC
that pulled this up also powered from the RAM battery?  If not, it might
get pulsed as power fails to the IC that pulls it up.  Very strange things
happen to digital ICs as the voltage drops towards 0.  This might be random
enough to explain your problems as well.  Think of what happens to the
processor as it loses power.  Do you want it to be running a program?  Nooo.

In fact, all of the circuitry that isolates the RAM must be powered by the 
battery.  If it's CMOS this won't be a power consumption problem.  Just make 
sure it runs at the voltage supplied by the battery (3V, I presume).

As Henry Spencer said, it might be easier just to buy one of the chips
designed for this purpose, but you should be able to do it yourself.
That's the hardware hacking spirit.

If you're really concerned about detecting RAM corruption problems during
power cycling, put a CRC routine into the power-down code.  This can be
done in a few (~50) lines of assembly language on most processors.  I have
public-domain C source code and (never-tested) 80x86 assembly language
that I can e-mail or post if you want.  BTW, the same code checks on power-up.

		David Chapman

{known world}!decwrl!vlsisj!fndry!davidc
vlsisj!fndry!davidc@decwrl.dec.com