Path: utzoo!attcan!utgpu!jarvis.csri.toronto.edu!mailrus!ames!apple!versatc!leadsv!practic!vlsisj!davidc
From: davidc@vlsisj.VLSI.COM (David Chapman)
Newsgroups: sci.electronics
Subject: Re: SRAM Battery backup
Summary: it's the power supply difference
Keywords: SRAM, battery backup
Message-ID: <15229@vlsisj.VLSI.COM>
Date: 18 May 89 02:56:47 GMT
References: <662@serene.UUCP>
Reply-To: davidc@vlsisj.UUCP (David Chapman)
Organization: VLSI Technology Inc., San Jose, CA
Lines: 38

In article <662@serene.UUCP> gbell@pnet12.cts.com (Greg Bell) writes:
>johne@hpvcfs1.HP.COM (John Eaton) writes:
>>                                          ... It is extremely important 
>>that you guarentee that the ram is not accessed during powerdown because
>>even a read will cause its current to jump by a factor of about 30,000.
>
>Really?  A read will cause problems?  In other words, I need to jump to a
>location in the monitor EPROM before powering down (there's no way to get the 
>8031 to just "HALT".  Maybe driving RESET high and holding it would do)?  

The reason that power consumption rises is (as someone else already mentioned)
that you end up trying to power the rest of the circuit through the SRAM's
data lines.  This can do nasty things to your battery, like maybe make its
output voltage drop momentarily.  It could also damage the SRAM.

Remember, these circuits are not designed to work at 1-2 volts, even for a few
milliseconds as the circuit powers down.  You don't know what they will do.
Normally, you don't care because any state change is going to get lost when
power drops to 0.  Now you do care.  So in order to keep from frying or 
scrambling your SRAM, you must logically (if not electrically) isolate it from 
the rest of the circuit as soon as the power supply voltage starts to drop.
If you can keep the chip from being selected, that will prevent problems even
if the read line is being pulsed.

I hadn't thought of the CS2 line before (I _knew_ there were other control
lines besides the WR :-), but now I remember that some circuits (and chips)
use an active-high CS line as a battery backup isolater.  They put a 4.5V
sensor on it, and you tie it to Vdd (_not_ the battery).  As power drops the
SRAM cuts out.  This may be the salient feature of the SRAMs recommended
elsewhere, and might be included in the SRAM with its own battery on-board.  
Wrt the latter, I'd be worried if my system were to have a significant
lifetime (>3 years).  How do you know that the internal battery is dying
_before_ you lose data the next time you power down?

		David Chapman

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