Path: utzoo!utgpu!jarvis.csri.toronto.edu!rutgers!apple!versatc!mips!mash
From: mash@mips.COM (John Mashey)
Newsgroups: comp.arch
Subject: Re: Criteria ...
Message-ID: <20795@winchester.mips.COM>
Date: 31 May 89 18:52:03 GMT
References: <2368@ogccse.ogc.edu> <1464@cfa.cfa.harvard.EDU> <141@dg.dg.com> <m0fRxlf-0001fDC@mipon2.intel.com> <686@pitstop.West.Sun.COM>
Reply-To: mash@mips.COM (John Mashey)
Organization: MIPS Computer Systems, Sunnyvale, CA
Lines: 17

In article <686@pitstop.West.Sun.COM> jwest@pitstop.West.Sun.COM (Jeremy West) writes:
....
>straight myself. It is worthwile in that I can try out the things we have been
>told and get corrections on MIPS from John Mashey etc.

Actually, that reminds me: some DATA (from an unnamed source, but
usually reliable): the SRAM question earlier:
	Chip		clock	SRAM 
	SPARCstation1	20MH	25ns
	MIPS R3000	20Mhz	25ns
	SPARCsystem300	25Mhz	20ns	<- new data
	MIPS R3000	25MHz	20ns
-- 
-john mashey	DISCLAIMER: <generic disclaimer, I speak for me only, etc>
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