Path: utzoo!utgpu!jarvis.csri.toronto.edu!rutgers!apple!versatc!mips!mash
From: mash@mips.COM (John Mashey)
Newsgroups: comp.arch
Subject: Re: Register usage
Message-ID: <20796@winchester.mips.COM>
Date: 31 May 89 18:57:50 GMT
References: <259@mindlink.uucp> <25382@ames.arc.nasa.gov> <m0fRx4x-0001fDC@mipon2.intel.com> <1RcY6x#64Zq3Y=news@anise.acc.com> <3427@bd.sei.cmu.edu>
Reply-To: mash@mips.COM (John Mashey)
Organization: MIPS Computer Systems, Sunnyvale, CA
Lines: 18

In article <3427@bd.sei.cmu.edu> firth@sei.cmu.edu (Robert Firth) writes:
....
>of the handler.  Since hard real time people care about predictability
>next only to performance, this gives loads of grief.

Actually, some hard real time people care about predictability more than
performance.  Maybe some knowledgable R.T. folks out there might care
to post something about this: it's an important area, and one that
doesn't discussed here as much as it deserves.  In particular, there
are of course serious implications of going faster (which usually implies
more caching) and being less predictable (sometimes implied by caching).
Maybe some real time folks could post some references, or some descriptions
of the different flavors of real-time (as there are quite a few).
-- 
-john mashey	DISCLAIMER: <generic disclaimer, I speak for me only, etc>
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