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From: davidb@inmos.co.uk (David Boreham)
Newsgroups: comp.arch
Subject: Re: ESD protection (was Re: Do you have bandwidth?)
Keywords: protection static ESD
Message-ID: <1536@brwa.inmos.co.uk>
Date: 31 May 89 16:56:04 GMT
References: <407@bnr-fos.UUCP> <7766@thorin.cs.unc.edu> <418@bnr-fos.UUCP> <6658@cbmvax.UUCP> <396@dalcsug.UUCP> <18682@gumby.mips.COM> <1450@brwa.inmos.co.uk> <6951@cbmvax.UUCP>
Reply-To: davidb@inmos.co.uk (David Boreham)
Organization: INMOS Limited, Bristol, UK.
Lines: 17



In reply to Randell Jesup's comment on my posting about whether ESD
protection is a significant reason for chip--chip signals being slower
than on-chip :-

 The capacitance which I was refering to is the PCB trace capacitance
 and the input capacitance of the chips to be driven. This is typically
 20--50pf. I fail to see where you can get anywhere near that capacitance
 from any kind of pad protection circuit. 
 
 I'd be interested to know where the original idea about ESD protection
 slowing down device signals came from --- it sounds most bizarre.
-- 
David Boreham, INMOS Limited | mail(uk): davidb@inmos.co.uk or ukc!inmos!davidb
Bristol,  England            |      (us): uunet!inmos-c!davidb
+44 454 616616 ex 543        | Internet : @col.hp.com:davidb@inmos-c