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From: davidb@inmos.co.uk (David Boreham)
Newsgroups: comp.arch
Subject: ESD protection on CHIPS
Message-ID: <1538@brwa.inmos.co.uk>
Date: 31 May 89 20:39:13 GMT
Reply-To: davidb@inmos.co.uk (David Boreham)
Organization: INMOS Limited, Bristol, UK.
Lines: 32



Further to my (and others) postings about ESD protection circuitry and
whether or not it has an effect on the speed of chip to chip 
signals; I have been doing a bit of digging on the subject and present
the following :-

1) ESD circuitry adds a not insignificant capacitance to a device's
   inputs. Something of the order of 1-2pf on a nominal 4-5pf input
   is likely.

2) ESD circuitry used to be a lot worse for capacitance, especially
   old 4000 series CMOS.

3) Some designs are likely to be more optimised for low ESD-related
   capacitance than others. SRAMs are usually very good.

4) PCB trace capacitance is about 20pf/foot.

So it would seem that in a typical microprocessor system with a CPU
connected to four or five inputs, and a foot or so of trace that the
capacitance due to ESD circuitry might be about 10--20% .

Unfortunately removing the protection circuitry is not really on.
Firstly you need ESD protection during PCB assembly.
Secondly you can still zap devices which are not connected to the
edge of the board.

-- 
David Boreham, INMOS Limited | mail(uk): davidb@inmos.co.uk or ukc!inmos!davidb
Bristol,  England            |      (us): uunet!inmos-c!davidb
+44 454 616616 ex 543        | Internet : @col.hp.com:davidb@inmos-c