Path: utzoo!utgpu!jarvis.csri.toronto.edu!rutgers!apple!bbn!bbn.com!slackey
From: slackey@bbn.com (Stan Lackey)
Newsgroups: comp.arch
Subject: Re: E2000
Message-ID: <40778@bbn.COM>
Date: 1 Jun 89 18:58:13 GMT
References: <125@ssp1.idca.tds.philips.nl> <28200326@mcdurb>
Sender: news@bbn.COM
Reply-To: slackey@BBN.COM (Stan Lackey)
Organization: Bolt Beranek and Newman Inc., Cambridge MA
Lines: 14

In article <28200326@mcdurb> aglew@mcdurb.Urbana.Gould.COM writes:
>>Note that this is one of the first extant examples of building a more
>>powerful top end beyond a widespread VLSI micro architecture.
>>This is in interesting trend, which is just the opposite of earlier efforts,
>>i.e., people have often done VLSI CMOS versions of earlier
>>supermini & mainframe architectures.  [Maybe some citations from VAX-land,

>Actually, isn't the Alliant non-vector instruction set a Motorola 68K take-off?

It sure is!  68020 except for callm-rtm.  We set out to do 68881
compatibility as well, but ended up doing a proprietary scalar FP
architecture for implementation reasons.  Memory management is a
subset of the 68420 (sp?) MMGT chip.
-Stan