Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!csd4.milw.wisc.edu!lll-winken!uunet!tektronix!sequent!jjb
From: jjb@sequent.UUCP (Jeff Berkowitz)
Newsgroups: comp.arch
Subject: Re: Q-M tunneling limitations on feature size ?
Message-ID: <16346@sequent.UUCP>
Date: 21 May 89 17:24:42 GMT
References: <3810043@eecs.nwu.edu>
Reply-To: jjb@sequent.UUCP (Jeff Berkowitz)
Organization: Sequent Computer Systems, Inc
Lines: 19

In article <3810043@eecs.nwu.edu> naim@eecs.nwu.edu (Naim Abdullah) writes:
>Can anybody provide a ball park figure for a feature size that will cause
>quantum mechanical tunneling effects to cause a chip to malfunction ?
>
I recommend "Introduction to VLSI Systems", Mead & Conway, Addison-Wesley,
1980.  This old book is still a good way for people without a background
in semiconductors to at least get some appreciation of the issues.  In
chapter 1 Mead writes

	Finally, there appears to be a fundamental limit
	of approximately one-quarter micron channel length,
	where certain physical effects such a the tunneling
	through of the gate oxide...begin to make devices of
	smaller dimension unworkable.

Chapter nine has a more extensive discussion of the limits to scaling.
-- 
Jeff Berkowitz N6QOM			uunet!sequent!jjb
Sequent Computer Systems		Custom Systems Group