Path: utzoo!attcan!uunet!mcvax!ukc!dcl-cs!aber-cs!pcg
From: pcg@aber-cs.UUCP (Piercarlo Grandi)
Newsgroups: comp.arch
Subject: Re: 80486 vs. 68040 code size [really: how many regs]
Summary: A register by any other name...
Message-ID: <965@aber-cs.UUCP>
Date: 21 May 89 11:05:58 GMT
Reply-To: pcg@cs.aber.ac.uk (Piercarlo Grandi)
Distribution: eunet,world
Organization: Dept of CS, UCW Aberystwyth
	(Disclaimer: my statements are purely personal)
Lines: 23

In article <8125@killer.Dallas.TX.US> elg@killer.Dallas.TX.US (Eric Green)
writes (let's pick just one!):
    
    I've read the CRISP paper, and several other stack-stack papers. In
    all of them they mention that caching the top <n> entries of the stack
    in hardware registers was a Big Win performance wise. All I said was
    that a register is a register, whether it is accessed as a "stack" or
    explicitly as a register.

Too bad that there are non irrelevant differences between an explicitly
addressed set of registers used as stack cache and a stack cache, as far as
the whole system and the compiler are concerned. Also, too bad that usually
<n> is not that large :-), and in the range of the number of useful registers
in a register bank.

As somebody never tires to point out (Brian Case, if my memory serves me
correctly), three ported register files, from a CPU designer's point of view,
are a big win, whether you access them from the architecture as stack cache
or bank of registers and there is a good case for the stack cache argument.
-- 
Piercarlo "Peter" Grandi           | ARPA: pcg%cs.aber.ac.uk@nsfnet-relay.ac.uk
Dept of CS, UCW Aberystwyth        | UUCP: ...!mcvax!ukc!aber-cs!pcg
Penglais, Aberystwyth SY23 3BZ, UK | INET: pcg@cs.aber.ac.uk