Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!tut.cis.ohio-state.edu!cs.utexas.edu!uunet!cbmvax!jesup
From: jesup@cbmvax.UUCP (Randell Jesup)
Newsgroups: comp.arch
Subject: Re: ESD protection (was Re: Do you have bandwidth?)
Keywords: protection static ESD
Message-ID: <6951@cbmvax.UUCP>
Date: 23 May 89 03:17:23 GMT
References: <407@bnr-fos.UUCP> <7766@thorin.cs.unc.edu> <418@bnr-fos.UUCP> <6658@cbmvax.UUCP> <396@dalcsug.UUCP> <18682@gumby.mips.COM> <1450@brwa.inmos.co.uk>
Reply-To: jesup@cbmvax.UUCP (Randell Jesup)
Organization: Commodore Technology, West Chester, PA
Lines: 18

In article <1450@brwa.inmos.co.uk> davidb@inmos.co.uk (David Boreham) writes:
>Several posters have refered to removing ESD protection on chip
>pads, and alluded to consequent speed advantages. Mabe I'm missing
>something but as far as I know the reason why off-chip signals are
>slower than on-chip ones is a combination of the following:
>
>1) Much larger capacitance (25pf minimum or 50--100 pf for busses).
...
>I think these are probably ranked in order of importance. ESD must surely
>be less important than these.

	Actually, I believe ESD is the prime reason for (1) above, so it
is the biggest target (for very high speed designs).

	Of course, I'm just a software guy, what do I know?  ;-)

-- 
Randell Jesup, Commodore Engineering {uunet|rutgers|allegra}!cbmvax!jesup