Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!tut.cis.ohio-state.edu!ucbvax!amdcad!rpw3
From: rpw3@amdcad.AMD.COM (Rob Warnock)
Newsgroups: comp.arch
Subject: Re: Register usage
Message-ID: <25720@amdcad.AMD.COM>
Date: 23 May 89 07:08:27 GMT
References: <259@mindlink.UUCP> <8104@killer.Dallas.TX.US> <25633@amdcad.AMD.COM> <25635@amdcad.AMD.COM> <3355@orca.WV.TEK.COM>
Reply-To: rpw3@amdcad.UUCP (Rob Warnock)
Organization: [Consultant] San Mateo, CA
Lines: 47

In article <3355@orca.WV.TEK.COM> andrew@frip.WV.TEK.COM writes:
+---------------
| [On the original 29k chips, which had no byte load/store:]
| 	"Anyway, the compilers have always handled 29k byte-load and byte-store
| 	... And Unix doesn't care ..."
| My Unix kernel device drivers sure care!  I have to talk to peripheral chips,
| some of whose registers require word-wide load/store and some of which require
| byte-wide.  I can't implement byte-wide with word-wide because of the side
| effects.  The extra logic to solve this problem is not pretty.
+---------------

True, which was why they changed the chip.

But note that the byte-access bits came out to the pins, even on the
"non-byte-read/write" chips. That is, even though the memory interface
was nominally word-wide, the byte indicators in the load and store
instructions and the LSBs of the addresses came out, and could be used
by external hardware, if desired. So assembly-language code could always
do the right thing. It's just that the code generated by the earlier C
compilers couldn't, since they "knew" that "all" memory was word-wide.
[And now that's fixed, so it's moot.]

By the way, another common trick [used even on other CPUs, such as 68000's]
was to simply put byte-wide chips on one byte rail on the bus (pick one...
for a couple of reasons, the *high*-order usually turned out to be the most
convenient on the 29k), and to "don't care" the LSBs of the CPU. That is,
wire CPU A2 to I/O chip A0, etc. Then, simply write the device header file
to name the I/O chip's registers as being 4 bytes apart...

+---------------
| The 29k looks like a nice chip, though, if you deal only with well-behaved
| peripheral interfaces.
+---------------

And the fact that the lockstep instruction pipelining is "exposed"
to the programmer means that (at least in the present 29k family)
you can predict what sequence of bus accesses a given instruction
sequence will generate, which also makes it really nice when dealing
with not-so-well-behaved interfaces...


Rob Warnock
Systems Architecture Consultant

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