Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!tut.cis.ohio-state.edu!purdue!ames!ncar!boulder!unicads!les
From: les@unicads.UUCP (Les Milash)
Newsgroups: comp.arch
Subject: Re: Criteria ... [really: California & Texas slug it out]
Message-ID: <464@unicads.UUCP>
Date: 23 May 89 21:36:31 GMT
References: <19088@winchester.mips.COM> <230@ross.UUCP> <20210@winchester.mips.COM>
Reply-To: les@unicads.UUCP (Les Milash)
Organization: Unicad  Boulder, CO
Lines: 25

In the midst of a lively debate, folks started talking about:
>>Consider that the 25Mhz R3000 requires two bus transactions per clock 
>>cycle, effectively running the bus at 50Mhz.
in the interest of educating ME, what's a "bus transaction"?

my guesses are:
	perhaps some bus that's common for R3000s is multiplexed, sending
	addr and data in two wads, and so it means the time it takes signals to 
	travel and be latched, although multiplexing the bus in a fast box seems
	nuts.

	or perhaps there's some additional signalling, for like multimaster
	arbitration or cache coherency protocols, and we're talking about this
	process.

	or maybe we're just talking about the time it takes some bus driver to
	charge up the bus, and a read cycle takes 2 of them, and maybe that's
	the limiting factor with cmos drams and cmos "c"pu's--i dunno.

	or ... ... duhhhhh?

in other words, is a bus "transaction" any more exalted a thing than a
bus "cycle"?

Les