Newsgroups: comp.arch
Path: utzoo!henry
From: henry@utzoo.uucp (Henry Spencer)
Subject: Re: DMA on RISC-based systems
Message-ID: <1989May26.170247.1165@utzoo.uucp>
Organization: U of Toronto Zoology
References: <46500067@uxe.cso.uiuc.edu>
Date: Fri, 26 May 89 17:02:47 GMT

In article <46500067@uxe.cso.uiuc.edu> sandrock@uxe.cso.uiuc.edu writes:
>In particular I am interested in the notion that the DECsystem 3100 has
>no DMA to its main memory, but instead relies upon the CPU to copy i/o
>buffers to/from an auxilliary memory. First, is this statement accurate?
>And second, if true, is this a reasonable tradeoff to make on a RISC system?

Not infrequently, a fast, well-designed CPU can copy data faster than all
but the very best DMA peripherals.  The DMA device may still be a net win
if it can use the memory while the CPU is busy elsewhere, giving worthwhile
parallelism, but this depends on how hard the CPU works the memory.  The
bottleneck nowadays is usually memory bandwidth rather than CPU crunch, and
caches aren't a complete solution, so DMA may end up stalling the CPU.
If that happens, it's not clear that DMA is worth the trouble, especially
since it's easier to design memory to serve only one master.

Having the CPU do the copying is not an obviously *un*reasonable idea.
Much depends on the details.

DMA historically was more popular than auxiliary memory because memory was
expensive.  This is no longer true.
-- 
Van Allen, adj: pertaining to  |     Henry Spencer at U of Toronto Zoology
deadly hazards to spaceflight. | uunet!attcan!utzoo!henry henry@zoo.toronto.edu