Path: utzoo!utgpu!jarvis.csri.toronto.edu!rutgers!apple!oliveb!mipos3!omepd!mcg From: mcg@mipon2.intel.com Newsgroups: comp.arch Subject: Re: High Level CPU Architectures Message-ID: Date: 30 May 89 01:09:24 GMT References: <1153@harrier.ukc.ac.uk> Sender: news@omepd.UUCP Reply-To: mcg@mipon2.UUCP (Steven McGeady) Organization: Intel Corp., Hillsboro Lines: 37 In article grunwald@flute.cs.uiuc.edu writes: > >BiiN, an Intel and Siemanns spinoff is producing a chip, based on the >80960 I think, that includes fault tolerence features ``from the >'432''. The fault-tolerant features are also provided in the 960MC, documentation for which is available from your friendly Intel sales droid. The interesing aspect of the BiiN chip is an object-oriented, capability- based addressing and memory-management scheme. This has allowed them to implement an operating system with network-wide VM in a 56-bit address space (24 bits of object number, 32 bits of address space per object). Objects are simple, paged, or bi-paged. A variety of protection mechanisms are implemented. The architecture appears to be sufficient to implement a secure operating system. Many of the things that people have been gushing about for years in this group and unix-wizards such as mapping files (and everything else) into the address space has already been implemented by the BiiN folks. Their files are all just objects, which are either passive (on disk) or active (in memory). While I did not work on the 432, I will say that while the 432 and 960 shared some engineers, the architects were completely different. This is not a discourse on BiiN's system - for more information, give them a call. S. McGeady Intel Corp. [I am not an employee of BiiN, though I do work on the 960 processor. The information presented here has previously been made public, and is available to anyone by calling BiiN. My comments do not represent an official statement by Intel Corp.]