Path: utzoo!attcan!uunet!mcvax!hp4nl!philapd!ssp1!roelof From: roelof@idca.tds.PHILIPS.nl (R. Vuurboom) Newsgroups: comp.arch Subject: E2000 Summary: 68k compatible, high-performance, Edgcore, Edge Keywords: 68k compatible, high-performance, Edgcore, Edge Message-ID: <125@ssp1.idca.tds.philips.nl> Date: 30 May 89 07:21:56 GMT Distribution: comp.arch Organization: Philips Telecommunication and Data Systems, The Netherlands Lines: 80 In article <20149@winchester.mips.COM> mash@mips.COM (John Mashey) writes: > And while I'm at it, there are rumors on the > street of Chapter-11 time for Edgecore(?) (used to be Edge). Anybody > have any data on that one? My info is that Edgcore (formerly Edge until it ran afoul of Leading Edge) has cut back on its own complete system activities and will concentrate on supplying OEMers with high-performance 68k cpu subsystems. There's an interesting architectural > connection: Edge's business is selling very-high-end > 68K-compatible boxes built from (I think) CMOS gate arrays, i.e., > boxes OEMed to cover the high end of your line, if you're 68K-based. > (i.e., this is a strategy somewhat similar to NexGen's for the 386, > I think). Any postings of data might be useful. The high end of our P9000 series motorola based line (the P9600) uses the E2000 cpu. This machine is currently in the (final) alpha testing phase. Although we're the first large European company to bring an E2000 based system to market we will not be the only large European company to do this. In other words, rumours of Edgcores demise are - at the very least - premature/overly optimistic (depending on your point of view). Now for some data: The E2000 CPU runs at around 15-16 VAX mips sustained. We get about 4x performance improvement over our 25 Mhz 68030 model. The machine can currently support 96Mb physical memory (4 triple Euro 32 Mbyte boards) but can be configured to 1 Gbyte physical memory when the (4M) chips become available. The cpu is 68010 compatible but has a number of the more frequently used 68020 instructions on board e.g long divide and multiply, scaled index addressing. Binaries on our lower end models (compiled in 68010 mode) run unchanged on the P9600. Although we don't support it instruction emulation can be used to run full 68020 code. The cpu is dual-pipelined (4-stage instruction fetch pipeline/5-stage operand execution pipeline) which permits a risc-like average instruction time of about 1.4 cycles per instruction. Cycle time is 45 ns. Virtual addressing space is 4Gbyte per process. The system is scalable with up to 4 processors (although we currently support only 1). Each cpu has a 32K 2 set associative virtual instruction cache with 16 byte line, a 448K direct mapped physical operand cache (meant for process stacks) and a 64K 4 set associative physical operand cache. The operand caches use a copy-back strategy. The distributed hardware cache coherency protocol is totally hardware controlled. It also has a branch prediction unit which contains a branch cache for 4K entries and a 16 entry lifo return stack, which together support correct branch prediction over 90% of the time. The subsystem has two busses: a proprietary 64 bit bus with a bandwidth of 128 Mb/s and a 20 Mb/s VMEbus which supports a 68020 support processor (used for boot and debug activities). It can support up to 5 secondary i/o busses. This is how we use the system: basically we pull out the processor card out of one of our lower model computers drop in the secondary bus card which attaches to the E2000 subsystem (in a separate cabinet). The lower model computer now becomes a io cabinet. Using this technique we can field upgrade a system in under 30 minutes - hardware and software. The cpu is implemented using five 1.5 micron 50000 CMOS gate arrays on a triple euro board, the data caches are on a separate triple euro board together with the mmu which supports a subset of the 68030 mmu functionality. Most of this info can be found in an article in Electronics, September 3 1987. Disclaimer 1: Opinions are mine, for my employers you pay extra. Disclaimer 2: I am _not_ an (ex-)80386 designer and my name does _not_ appear on Rev 1.0 ;-). -- Roelof Vuurboom SSP/V3 Philips TDS Apeldoorn, The Netherlands +31 55 432226 domain: roelof@idca.tds.philips.nl uucp: ...!mcvax!philapd!roelof