Path: utzoo!attcan!utgpu!jarvis.csri.toronto.edu!rutgers!apple!amdcad!crackle!tim
From: tim@crackle.amd.com (Tim Olson)
Newsgroups: comp.arch
Subject: Re: When is a RISC not a RISC {was Scoreboarding HW is simple}
Message-ID: <25783@amdcad.AMD.COM>
Date: 30 May 89 13:40:54 GMT
References: <19433@obiwan.mips.COM> <5004@pt.cs.cmu.edu> <m0fRxRp-0001fDC@mipon2.intel.com>
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In article <m0fRxRp-0001fDC@mipon2.intel.com> mcg@mipon2.UUCP (Steven McGeady) writes:
| Perhaps also 3-operand register-register normal instructions.  The number
| of cycles of latency caused by an instruction is an implementation, not
| an architectural feature (at least on the 960, this is not true of some
| other RISCs) - an upcoming version of the 960 has predominantly one-cycle
| latency instructions.

This brings up an interesting question.  I believe that in the
960{KA,KB,MC} part(s), the register file is 1-read, 1-write.  This means
that 3-operand instructions can execute in a single cycle only if one of
the operands is directly forwarded from the previous ALU operation --
otherwise, it takes 2 cycles just to read the operands.  Could you
discuss the tradeoffs behind the decision not to support 2 read ports? 
What frequency of pipeline stalls are caused by having to double-cycle
the register file?


	-- Tim Olson
	Advanced Micro Devices
	(tim@amd.com)