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From: brooks@vette.llnl.gov (Eugene Brooks)
Newsgroups: comp.arch
Subject: Re: Register usage
Message-ID: <26145@lll-winken.LLNL.GOV>
Date: 31 May 89 03:51:40 GMT
References: <259@mindlink.UUCP> <25382@ames.arc.nasa.gov> <m0fRx4x-0001fDC@mipon2.intel.com>
Sender: usenet@lll-winken.LLNL.GOV
Reply-To: brooks@maddog.llnl.gov (Eugene Brooks)
Organization: Lawrence Livermore National Laboratory
Lines: 13

In article <m0fRx4x-0001fDC@mipon2.intel.com> mcg@mipon2.UUCP (Steven McGeady) writes:
>The cut line is different on every architecture - 32 is sufficient on the
>960, but I am not disagreeing with Wall's estimate of 64.  Certainly
>in floating-point intensive scientific applications dominated by
>double-precision arithmetic in loops, more registers are needed.  But
>substantialy more than 64 seems to limit architectural flexibility
>quite severely.
The cut line for scratch registers is directly proportional to the memory
latency.  The longer your latency the more registers, and concurrently
handled computation, you need to mask it.


brooks@maddog.llnl.gov, brooks@maddog.uucp