Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!ames!ames.arc.nasa.gov!lamaster
From: lamaster@ames.arc.nasa.gov (Hugh LaMaster)
Newsgroups: comp.arch
Subject: Re: E2000
Keywords: 68k compatible, high-performance, Edgcore, Edge
Message-ID: <26207@ames.arc.nasa.gov>
Date: 31 May 89 19:06:53 GMT
References: <125@ssp1.idca.tds.philips.nl> <20752@winchester.mips.COM>
Sender: usenet@ames.arc.nasa.gov
Distribution: comp.arch
Organization: NASA - Ames Research Center
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In article <20752@winchester.mips.COM> mash@mips.COM (John Mashey) writes:

>Note that this is one of the first extant examples of building a more
>powerful top end beyond a widespread VLSI micro architecture.

>This is in interesting trend, which is just the opposite of earlier efforts,

I agree.  I would like to make a request here- I think the time has come
for micro people to consider mainframe architectural requirements.  Some
nice micros have come out in recent years which could have been extended
to mainframe architectures except for various flaws which, if remedied, would
have had little or no effect on the performance or usability as micros.

Next time, while designing a new architecture, ask if anything will stop you
from building a high performance implementation with:

a clearly and completely defined instruction set architecture 
support for a large number of processors in a symmetric arrangement
separate caches for each processor
a high bandwidth multi-port multi-bank central memory
high bandwidth I/O
provable encapsulation/virtualization

It is my belief that adding the above would cost little, but would buy
potential customers a great deal.  I note that some recent micros my
indeed be capable of all of the above, but not all of them do.




  Hugh LaMaster, m/s 233-9,  UUCP ames!lamaster
  NASA Ames Research Center  ARPA lamaster@ames.arc.nasa.gov
  Moffett Field, CA 94035     
  Phone:  (415)694-6117