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From: mash@mips.COM (John Mashey)
Newsgroups: comp.sys.intel
Subject: Re: Dhrystones/Whetstones for i860
Message-ID: <20566@winchester.mips.COM>
Date: 27 May 89 22:42:39 GMT
References: <212@riunite.ACA.MCC.COM> <494@sns4.fpssun.fps.com>
Reply-To: mash@mips.COM (John Mashey)
Organization: MIPS Computer Systems, Sunnyvale, CA
Lines: 51

In article <494@sns4.fpssun.fps.com> lfm@sns4.UUCP (Larry Meadows ) writes:

>From intel published material:
>Dhrystones:
>	Measured 69,000 Dhrystones (V1.1) @ 33.3 MHz 
>	  Green Hills C V1.8.5
>	  Estimated 90K (V1.1) and 85K(V2.1) @ 40MHz w/ improved compiler
>Whetstones:
>	Measured 20Kwhets (double) and 25.6 Kwhets (double) @ 33.3 Mhz
>	  Green Hills Fortran 1.8.5
>	  Estimated 25 and 32 Kwhets @ 40MHz w/ improved compiler
>Linpack 100x100 (Double precision):
>	6.1 Mflops (compiled), 11 (coded BLAS) @33.3MHZ
>	  Green Hills Fortran 1.8.5 and VAST 2.25N1 (vectorizer)
>	  Estimated 10 and 13.2 Mflops @40MHz w/ improved compiler
>
>Several compiler optimization switches were used when compiling these
>benchmarks.  Note that these numbers have been available for some time.

Note that Greenhills C compilers sometimes include a "Dhrystone" switch that
inlines strcpy [this was a long topic of discussion in comp.arch.]
Whether or not Intel used this is unclear.  [The March 89 i860 performance
document says it uses "-OLM -X405 -X370 -X393 -X422": if anybody knows
what that means, please post!}

However, it's an optimization 
that might be worth at most 1% on real programs, that happens, on this one
to boost your Dhrystone numbers by about 30%.  The author of the benchmark
states that you cannot make good interpretations of Dhrystone results
without seeing the output of the compiler.....  I.e., given that there is
an optimization that 1) most people would not turn on in normal code,
and that 2) boosts performance 30%, the number has lost all predictive power
in the absence of looking at the code.

Given that fact that Dhrystone numbers are now meaningless without the
generated code, Michael Slater of Microprocessor Report is collecting
the code from vendors and hopefully will publish his analysis of what's
going on.

re: Linpack: you may have missed that LINPACK was simulated (which is OK),
but used zero-wait state external memory (@ 40MHz).  Since LINPACK does not fit
in the on-chip caches (unlike the others) it remains to be seen what the
actual performance will be in buildable machines......

Anyway, the Whetstone numbers look pretty reasonable, and not too surprising;
it's hard to tell what the Dhrys and Linpacks really mean, yet.
-- 
-john mashey	DISCLAIMER: <generic disclaimer, I speak for me only, etc>
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