Path: utzoo!attcan!uunet!cbmvax!jesup
From: jesup@cbmvax.UUCP (Randell Jesup)
Newsgroups: comp.arch
Subject: Re: ESD protection on CHIPS
Message-ID: <7036@cbmvax.UUCP>
Date: 1 Jun 89 19:29:30 GMT
References: <1538@brwa.inmos.co.uk>
Reply-To: jesup@cbmvax.UUCP (Randell Jesup)
Organization: Commodore Technology, West Chester, PA
Lines: 32

In article <1538@brwa.inmos.co.uk> davidb@inmos.co.uk (David Boreham) writes:
>1) ESD circuitry adds a not insignificant capacitance to a device's
>   inputs. Something of the order of 1-2pf on a nominal 4-5pf input
>   is likely.

	Sounds reasonable, I guess.

>3) Some designs are likely to be more optimised for low ESD-related
>   capacitance than others. SRAMs are usually very good.
>
>4) PCB trace capacitance is about 20pf/foot.

	The systems I was involved in were 40Mhz systems, and used Augat
PCBs for low capacitance.  Even then, the amount of memory we could add was
mainly limited by the capacitance associated with the RAMs.  (These were
64Kbit statics, 15ns, in 1987 or so).  Reducing ESD capacitance on our chips
and the rams would have been a big improvement, according to the system
designer and chip guys (I'm a software person, so I take their word about
such things).

>Unfortunately removing the protection circuitry is not really on.
>Firstly you need ESD protection during PCB assembly.
>Secondly you can still zap devices which are not connected to the
>edge of the board.

	Which is the reason I said that new interconnect (non-PCB) and
packaging technologies were needed.  I hear TAB helps some, but not with
everything.


-- 
Randell Jesup, Commodore Engineering {uunet|rutgers|allegra}!cbmvax!jesup