Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!tut.cis.ohio-state.edu!rutgers!sun-barr!ames!ames.arc.nasa.gov!lamaster
From: lamaster@ames.arc.nasa.gov (Hugh LaMaster)
Newsgroups: comp.arch
Subject: Re: DMA on RISC-based systems
Message-ID: <26461@ames.arc.nasa.gov>
Date: 5 Jun 89 17:17:32 GMT
References: <46500067@uxe.cso.uiuc.edu> <28200325@mcdurb> <2819@scolex.sco.COM>
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Organization: NASA - Ames Research Center
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In article <2819@scolex.sco.COM> seanf@scolex.UUCP (Sean Fagan) writes:
>In article <28200325@mcdurb> aglew@mcdurb.Urbana.Gould.COM writes:

>>Smarter and faster. One of the big problems with smart I/O is that it is done
>>using slow microprocessors 1 or 2 generations old. Now, if your smart I/O

>Well, more than 20 years ago, a machine was built which had smart I/O
>processors.  Just for the sake of fun, let's call the central processor a
>"CP," and the I/O processors "PP"'s.  Fun, huh?  Now, the "CP" was 60-bits,
>had something like 70-odd instructions, and was a load-store/3-address
>This machine *screamed*.  It had, for the time, an incredibly fast processor


>(the "CP"), which, even today, will outperform things like Elxsi's.  With

>For those of you who haven't guessed, the machine was the CDC Cyber,

There were two rather distinct flavors of Cybers.  The main distinguishing
feature was the kind of peripheral processors the machine had. (A
hybrid- the Cyber 176 could accept both kinds.)

The PP's in the 7600 ("upper Cyber") did *not* write to any
designated memory, but instead to dedicated memory locations, just like, in
effect, the on-board buffers previously referred to in some postings.  These
PP's would interrupt the CPU *every few hundred words* of I/O to *copy* the
data from one group of memory locations to another.  Strangely enough, this
gave the ~20 VAX MIPS (please, let's argue about the exact rating off-line)
7600 (which was about 2X the similar "lower Cyber" 760) the fastest I/O
around of any commercial machine for many years.  So, is DMA a "good idea"? -
it depends.  Overall, you may get more performance for your dollar that way.  

The PP's on the lower Cybers (6600-Cyber 760) could write to any memory
location, and could make your coffee for you in the morning too.  The NOS
operating system had major pieces in the PP's, and PP saturation was the
usual bottleneck, rather than CPU saturation.  You could keep about twice as
many people happy per CPU "MIP" (whatever that is) on the Cybers, because of
all the hidden MIPS in the PP's, compared with, say, a VAX-11/7xx or similar
machines. 

So, within the Cyber line, you had two examples of both extremes:

A machine where the CPU had to copy data (7600), and, machines
where not only smart I/O, but other major pieces of the system ran in the PP's.
Both architectures worked successfully, especially with respect to performance,
and only came to grief after many years over the wierd word size 
and lack of virtual memory and memory address space.



  Hugh LaMaster, m/s 233-9,  UUCP ames!lamaster
  NASA Ames Research Center  ARPA lamaster@ames.arc.nasa.gov
  Moffett Field, CA 94035     
  Phone:  (415)694-6117