Path: utzoo!utgpu!jarvis.csri.toronto.edu!rutgers!rochester!pt.cs.cmu.edu!b.gp.cs.cmu.edu!jsp
From: jsp@b.gp.cs.cmu.edu (John Pieper)
Newsgroups: comp.arch
Subject: fast memories (war superscalar)
Message-ID: <5128@pt.cs.cmu.edu>
Date: 5 Jun 89 19:22:41 GMT
Reply-To: jsp@b.gp.cs.cmu.edu (John Pieper)
Distribution: usa
Organization: Carnegie-Mellon University, CS/RI
Lines: 19
Keywords:


Why should we go to custom memory chips?

With an on-chip cache, there are several ways to implement fast memory without
going to custom chips. The processor needs to support out-of-order memory
operations to support some of the fancier optimizations, but given this,
page-mode DRAMS can be interleaved to give you very good performance,
especially if you have an on-chip cache and load a line at a time.

Without this, a harvard architecture can use page-mode to get cache-like
speeds for the instruction stream, and a fancier interleaved scheme for data
accesses.

Why bend over backwards (inter-company contracts, risk, design cost, etc)
for a 100% when you can have an easy 90% solution? The marginal gain isn't
worth it.
-- 
John Pieper				 jsp@cs.cmu.edu
School of Computer Science,  Carnegie-Mellon University
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