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From: brooks@maddog.llnl.gov (Eugene Brooks)
Newsgroups: comp.arch
Subject: Re: fast memories (war superscalar)
Message-ID: <26469@lll-winken.LLNL.GOV>
Date: 6 Jun 89 05:07:17 GMT
References: <5128@pt.cs.cmu.edu> <26450@lll-winken.LLNL.GOV>
Sender: usenet@lll-winken.LLNL.GOV
Reply-To: brooks@maddog.llnl.gov (Eugene Brooks)
Distribution: usa
Organization: Lawrence Livermore National Laboratory
Lines: 16

In article <26450@lll-winken.LLNL.GOV> brooks@maddog.llnl.gov (Eugene Brooks) writes:
>>With an on-chip cache, there are several ways to implement fast memory without
>>going to custom chips. The processor needs to support out-of-order memory
>>operations to support some of the fancier optimizations, but given this,
>>page-mode DRAMS can be interleaved to give you very good performance,
>>especially if you have an on-chip cache and load a line at a time.
>The latest and greatest VLSI micros utilize "page mode" drams and those
>page mode drams are not fast enough.
Sorry about this piece of brain damage I read the posting too quickly
I shouldn't have responded to this as my point was that the interleaving several
chips raises the cost of the memory system and this was the reason to interleave
directly on the chip.  If the micro chips capable of 60 MFLOP floating rates are not
custom, the memory chips to go with them are not custom either.


brooks@maddog.llnl.gov, brooks@maddog.uucp