Path: utzoo!attcan!utgpu!jarvis.csri.toronto.edu!rutgers!apple!bbn!bbn.com!slackey
From: slackey@bbn.com (Stan Lackey)
Newsgroups: comp.arch
Subject: Re: fast memories (war superscalar)
Message-ID: <40985@bbn.COM>
Date: 6 Jun 89 14:41:04 GMT
References: <5128@pt.cs.cmu.edu> <26450@lll-winken.LLNL.GOV>
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Reply-To: slackey@BBN.COM (Stan Lackey)
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Organization: Bolt Beranek and Newman Inc., Cambridge MA
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In article <26450@lll-winken.LLNL.GOV> brooks@maddog.llnl.gov (Eugene Brooks) writes:
>In article <5128@pt.cs.cmu.edu> jsp@b.gp.cs.cmu.edu (John Pieper) writes:
>>
>>Why should we go to custom memory chips?
>Memory chips which are built to be compatible with a high performance
>micro destined for commodity use won't be "custom."

There are already many custom memory chips.  Cache tag RAM's, video RAM's
and the like all started out that way.  The 88200 is a custom memory
chip.  An extremist (like me) might consider the i860 as a custom memory
chip.  :-)

What percentage of a chip should be memory cells in order for it to really
be a considered a custom memory chip?

>>page-mode DRAMS can be interleaved to give you very good performance,
>>especially if you have an on-chip cache and load a line at a time.

I have seen many applications (the big problems for which people want
the heavy iron) which don't utilize a cache well, even with a
half-megabyte cache.  For example, a matrix multiplication processes
one matrix down columns and the other across rows.  Some cases like this
can actually get poorer performance with a large line size.

>>Why bend over backwards (inter-company contracts, risk, design cost, etc)
>>for a 100% when you can have an easy 90% solution? The marginal gain isn't
The best case is where a company makes both the uP and the memory (88000
for example).
The gain isn't marginal, either.  You statements may be OK now, but next
generation will see the CPU in the 5 to 20ns range, with srams in the
20ns and drams in the 80ns range?  Clearly needs work.
-Stan  "Do I have an opinion yet?"