Path: utzoo!attcan!utgpu!jarvis.csri.toronto.edu!rutgers!cs.utexas.edu!sun-barr!sun!imagen!atari!portal!cup.portal.com!bcase
From: bcase@cup.portal.com (Brian bcase Case)
Newsgroups: comp.arch
Subject: Re: E2000 (Really Mainframe Architectures)
Message-ID: <19131@cup.portal.com>
Date: 5 Jun 89 16:18:28 GMT
References: <125@ssp1.idca.tds.philips.nl> <20752@winchester.mips.COM> <26207@ames.arc.nasa.gov> <184@dg.dg.com>
Organization: The Portal System (TM)
Lines: 27

>	Multiprocessor support
>
>	The ability to use 4 gigabytes of virtual memory (without
>	cludging the software around)
>
>	The ability to use 4 gigs of physical memory (without 
>	cludging the software around)

Robert (and anyone else), could you post something short that gives
examples of the software kludges needed?

>>Next time, while designing a new architecture, ask if anything will stop you
>>from building a high performance implementation with:
>
>>a clearly and completely defined instruction set architecture 
>>support for a large number of processors in a symmetric arrangement
>>separate caches for each processor
>>a high bandwidth multi-port multi-bank central memory
>>high bandwidth I/O
>>provable encapsulation/virtualization
>>It is my belief that adding the above would cost little, but would buy
>>potential customers a great deal.  I note that some recent micros my
>>indeed be capable of all of the above, but not all of them do.

Hugh (and anyone else), could you post a short summary of architectures
that don't have the above?  E.g., what is (and isn't) a clearly- and
completely-defined ISA?