Path: utzoo!attcan!utgpu!jarvis.csri.toronto.edu!mailrus!iuvax!uxc!garcon!garcon.cso.uiuc.edu!grunwald From: grunwald@flute.cs.uiuc.edu (Dirk Grunwald) Newsgroups: comp.arch Subject: Re: superscalar Message-ID: Date: 7 Jun 89 14:49:31 GMT References: <26356@lll-winken.LLNL.GOV> <14FU029t326G01@amdahl.uts.amdahl.com> <26434@lll-winken.LLNL.GOV> Sender: news@garcon.cso.uiuc.edu Reply-To: grunwald@flute.cs.uiuc.edu Organization: University of Illinois, Urbana-Champaign Lines: 11 In-reply-to: brooks@vette.llnl.gov's message of 5 Jun 89 18:34:22 GMT If I remember correctly, electron transport code is seperable, and ports well to distributed memory multi-processors right? Intel has plans to produce a successor the iPSC/2 based on the the i860, and finally using a reasonable I/O architecture. They plan to produce 2048-node systems for DARPA. -- Dirk Grunwald -- Univ. of Illinois (grunwald@flute.cs.uiuc.edu)