Path: utzoo!attcan!utgpu!jarvis.csri.toronto.edu!rutgers!tut.cis.ohio-state.edu!oscsuna.osc.edu!pixelpump.osc.edu!stein From: stein@pixelpump.osc.edu (Rick 'Transputer' Stein) Newsgroups: comp.arch Subject: Re: DMA on RISC-based systems Message-ID: <209@oscsuna.osc.edu> Date: 7 Jun 89 16:07:26 GMT References: <46500067@uxe.cso.uiuc.edu> <181@dg.dg.com> <1989May31.163057.543@utzoo.uucp> <3480@orca.WV.TEK.COM> <185@dg.dg.com> <620@biar.UUCP> <41042@bbn.COM> Sender: news@oscsuna.osc.edu Reply-To: stein@pixelpump.UUCP (Rick 'Transputer' Stein) Organization: Ohio Supercomputer Center Lines: 20 In article <41042@bbn.COM> slackey@BBN.COM (Stan Lackey) writes: >2) This discussion brings to mind one that went around some time ago, > which was, is it better to supply a bunch of specialized processors > (then bitblt's, now including DMA controllers), or a bunch of identical > processors connected together? Theory was, when the bitblt and DMA are > done, the other processor(s) can be applied to a compute bound task. > It seems to me this might make an interesting product; price/perf > range is varied by the number of [identical] processors, and all I/O > hardware is very very dumb. > >-Stan This sure sounds like an physically objective parallel i/o mechanism. A processor controlling some portion of the i/o stream as mapped to a specific device. Sounds like a job for Transputer Man! :-). -=- Richard M. Stein (aka Rick 'Transputer' Stein) Concurrent Software Specialist @ The Ohio Supercomputer Center Ghettoblaster vacuum cleaner architect and Trollius semi-guru Internet: stein@pixelpump.osc.edu, Ma Bell Net: 614-292-4122