Path: utzoo!attcan!utgpu!utstat!jarvis.csri.toronto.edu!rutgers!apple!vsi1!wyse!mips!rogerk
From: rogerk@mips.COM (Roger B.A. Klorese)
Newsgroups: comp.arch
Subject: Re: RISC list
Message-ID: <21319@abbott.mips.COM>
Date: 9 Jun 89 02:22:35 GMT
References: <1173@cbnewsc.ATT.COM> <1447@ncr-sd.SanDiego.NCR.COM>
Reply-To: rogerk@servitude.mips.COM (Roger B.A. Klorese)
Organization: MIPS Computer Systems, Sunnyvale, CA
Lines: 23
Summary:

In article <1447@ncr-sd.SanDiego.NCR.COM> steves@ivory.SanDiego.NCR.COM (Steve Schlesinger x2150) writes:
>In article <1173@cbnewsc.ATT.COM> levy@cbnewsc.ATT.COM (Daniel R. Levy) writes:
>>Accel		(Celerity)
>	The RISC in the Celerity products was designed and built by
>	NCR - the NCR/32.  Celerity added register window and floating
>	point and other HW around the NCR/32.

...but the NCR/32 is a RISC-come-lately in that it wasn't till the Celerity
boys hung the register stack cache, etc, around it and ignored the 370-type
added instruction set that the processor could be claimed to be any sort of
general-purpose RISC.

>	The last Celerity product developed an ECL version of a subset
>	of the NCR/32.

(a) Yes, the RISC subset.
(b) "The last Celerity product" is on the market as the FPS-500 from FPS
    Computing.
-- 
ROGER B.A. KLORESE      MIPS Computer Systems, Inc.      phone: +1 408 720-2939
928 E. Arques Ave.  Sunnyvale, CA  94086             voicemail: +1 408 991-7802
{ames,decwrl,pyramid}!mips!rogerk                     rogerk@servitude.mips.COM
"I want to live where it's always Saturday."  -- Guadalcanal Diary