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From: bcase@cup.portal.com (Brian bcase Case)
Newsgroups: comp.arch
Subject: Re: fast memories (war superscalar)
Message-ID: <19257@cup.portal.com>
Date: 8 Jun 89 17:24:27 GMT
References: <5128@pt.cs.cmu.edu> <26450@lll-winken.LLNL.GOV> <40985@bbn.COM>
Distribution: usa
Organization: The Portal System (TM)
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>You[r] statements may be OK now, but next generation will see the CPU
>in the 5 to 20ns range, with srams in the 20ns and drams in the 80ns
>range?  Clearly needs work.

And some of that work is being done now.  True, processors will be at
50 MHz and beyond.  However, the contention that memories will not keep
up is not necessarily true.  I know of an experimental SRAM now being
fabbed that will have an access time of about 4 ns with a 16K x 4
organization and no on-chip address registers or other gunk.  One
problem:  the die is big (4mm x 6mm?).  I think Cypress is already
sampling a 4K SRAM in the same access-time neighborhood.  IBM said
they have a 22ns 1Mbit DRAM (although nobody can figure out how real
it is).

Memory latency is a problem, but to say that it won't be solved seems
alarmist.