Path: utzoo!attcan!utgpu!jarvis.csri.toronto.edu!rutgers!apple!bbn!bbn.com!slackey
From: slackey@bbn.com (Stan Lackey)
Newsgroups: comp.arch
Subject: Re: VAX Architecture (Was: Re: Slandering Intel)
Message-ID: <41188@bbn.COM>
Date: 9 Jun 89 18:50:54 GMT
References: <76700071@p.cs.uiuc.edu> <3335@cps3xx.UUCP> <19255@cup.portal.com>
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Reply-To: slackey@BBN.COM (Stan Lackey)
Organization: Bolt Beranek and Newman Inc., Cambridge MA
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In article <19255@cup.portal.com> bcase@cup.portal.com (Brian bcase Case) writes:
>>Out of curiousity, and not trying to start a new religious war, what
>>about the VAX architecture do you consider a failure?
>
>I'm not the original poster, but ....  The VAX is certainly not a
>commercial failure.  However, its instruction encodings are an
>abomination because they force a serial instruction decode.  If it
>takes 3 cycles just to decode an instruction, your only chance of
>achieving high performance is to speed up the clock.  But if you

You statement is correct for the 11/730 but incorrect for all the
other VAXes.  Even the 8200 chip set parses many combinations of
opcodes and specifiers in parallel; it is true that it could be done
better, just like anything that exists could have been done better.
It most certainly does not take three cycles to parse the opcode; at
most one cycle for the opcode, and one each per operand specifier.  In
many cases, opcode and first specifier, or even opcode and first two
specifiers, and parsed in parallel.

The CPI's you may have seen for the 11/780 were probably misleading,
depending upon what the reader was "looking for".  For example, three
of the average cycles-per-instruction are due to address translation
and cache misses.  NTS, all computers feel this one.  Note that the
'average' may not make much sense anyway; many instructions (the "RISC
subset") really only take a few cycles.  It's just that enough of the
multi-cycle ones are executed, and when they happen, take a long time,
and increase the average by a lot.

Early implementations also suffered by not havine enough bandwidth on
writes, and that mixed with instructions that have burst writes, added
maybe one cycle to the average CPI.  The "best" instruction set
encodement in the world does not fix this.
-Stan