Path: utzoo!utgpu!jarvis.csri.toronto.edu!rutgers!cs.utexas.edu!uunet!ficc!peter
From: peter@ficc.uu.net (Peter da Silva)
Newsgroups: comp.arch
Subject: Re: What is a Mainframe?
Keywords: high-performance
Message-ID: <4489@ficc.uu.net>
Date: 10 Jun 89 02:20:54 GMT
References: <125@ssp1.idca.tds.philips.nl> <20752@winchester.mips.COM> <21287@obiwan.mips.COM>
Distribution: comp.arch
Organization: Xenix Support
Lines: 18

In article <21287@obiwan.mips.COM>, keith@mips.COM (Keith Garrett) writes:
> peter, could you expound on this statement more. i can't think of anything
> that is intrinsically unique to the different classes of machines.

It's more a trend than anything intrinsically unique, but for a given CPU
speed you can generally do more I/O at the mainframe end of things. After
all, the micro has to feed the whole world through its I/O pins. A mini has
a bus and often a bunch of ribbon cables. A mainframe has multiple I/O
processors.

Compare and contrast static column caches in a micro like an AT/386 with
the multiple interleaved memory channels of a mainframe with the same
dhrystones rating.
-- 
Peter da Silva, Xenix Support, Ferranti International Controls Corporation.

Business: uunet.uu.net!ficc!peter, peter@ficc.uu.net, +1 713 274 5180.
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