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From: jxw@RODS.IUS.CS.CMU.EDU (John Willis)
Newsgroups: comp.arch,comp.lsi,comp.lsi.cad
Subject: Re: VHDL Simulator
Summary: RE: VHDL simulator
Keywords: VHDL
Message-ID: <5182@pt.cs.cmu.edu>
Date: 10 Jun 89 15:41:45 GMT
References: <6419@cs.Buffalo.EDU>
Distribution: na
Organization: Carnegie-Mellon University, CS/RI
Lines: 27

As part of a PhD project in parallel simulation of digital
systems, I have been adapting GNU compiler technology to
compile VHDL 1076 models into a (conservative) distributed
simulation environment.  There are currently three targets:
80386 uniprocessors running SYS V, SUN 3 workstations linked
by sockets, and an Encore (shared memory) multiprocessor.
There are no intentional omissions to the VHDL 1076 standard.
In addition, the simulator allows implementation of design
entities in terms of SCALD gate-level descriptions (but not
VALID or AIDA's behavioral modeling languages), and SCALD
logic macros can be defined in terms of VHDL entities.

I would very much appreciate access to large VHDL or SCALD
models (and stimuli) with which to stress the functionality 
and performance of the simulator.  Subject to successful
testing, I expect an initial release before the end of the
year.  Release should be under conditions similiar to GNU
software.  We are interested in feedback on both relative
and absolute performance under realistic load.

-John

Affiliation given for identification only...

The Robotics Institute, Carnegie-Mellon University
(412) 268 - 7018

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