Path: utzoo!utgpu!jarvis.csri.toronto.edu!rutgers!sun-barr!sun!imagen!atari!portal!cup.portal.com!ts
From: ts@cup.portal.com (Tim W Smith)
Newsgroups: comp.arch
Subject: Why did Intel do it this way?
Message-ID: <19324@cup.portal.com>
Date: 10 Jun 89 09:22:39 GMT
Organization: The Portal System (TM)
Lines: 19

The recent "discussion" here about the Intel processors has
reminded me of something I have wondered about for quite a
while.  I've asked about this on comp.sys.intel, but have
never received an answer, so I thought that I would ask here.

On the 80286 in protected mode, a segment register contains
13 bits of segment number and 3 bits of other stuff.  The
3 bits of other stuff are the least significant bits.

Why didn't they put those 3 bits as the most significant bits?
If they had, then by setting up the GDT and LDT properly, one
could have a linear address space.

Someone suggested to me once that perhaps they used the three
lower bits because the table that the segment number is used
to lookup in consists of 8 byte entries, and so they don't have
to do any shifting to generate the byte offset into the table.

						Tim Smith