Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!ames!oliveb!mipos3!mipos2.intel.com!sundar From: sundar@mipos2.intel.com (Sundar Iyengar~) Newsgroups: comp.arch Subject: Re: 386/486 Virtual Memory Question... Message-ID: <243@mipos3.intel.com> Date: 12 Jun 89 05:03:02 GMT Sender: news@mipos3.intel.com Reply-To: sundar@mipos2.intel.com (Sundar Iyengar~) Organization: Microprocessor Component Group, Intel Corp., Santa Clara, CA Lines: 48 In article , Hugh Brinkley Sprunt writes: > > The 386 and 486 architectures claim a virtual address space size of > 2^46 bytes. The virtual address is formed from a 14 bit selector > and a 32 bit offset. > b) This scheme gives us 2^14 independent address spaces of 2^32 > bytes each. In other words, the virtual memory scheme > consists of as many as 2^14 segments of 2^32 bytes each. > > If (b) is the answer, how does the processor communicate the 14 bits of > selector information to the memory mapping hardware/software? b) is the correct answer. Page 2-2 of the 80386 Programmer's Ref Manual says this: "Applications programmers view the logical address space of the 80386 as a collection of 16,383 one-dimensional subspaces, each with a specified length [ranging] from one byte upto a maximum of 2^32 bytes". The 14 bit selector information is held in a segment register. For code segments, the segment register is CS. For data segments DS, ES, FS and GS may contain the segment selector bits. The stack segment selector is SS. During code execution, the instructions are fetched from the code segment selected by CS. The data may come from any data segment selected by the four data segment registers. More than four data segments can be accessed by appropriately loading the data segment registers with selector information. The default segment selection is: CS for code SS for stack DS for local data ES for string instruction destinations Special instruction prefix elements may be used to override the default segment selection. So, to answer your question, "the processor [communicates] the 14 bits of selector information to the memory mapping hardware" by looking up the corresponding selector register. Sundar Iyengar Microprocessor Design UUCP: intelca!mipos3!mipos2!sundar Intel, SC4-59 ARPA: sundar@mipos2.intel.com 2625, Walsh Avenue CSNET: sundar@mipos2.intel.com Santa Clara, CA 95051 AT&T: O: (408) 765-5206