Path: utzoo!attcan!utgpu!jarvis.csri.toronto.edu!rutgers!cs.utexas.edu!sun-barr!decwrl!decvax!ima!johnl
From: johnl@ima.ima.isc.com (John R. Levine)
Newsgroups: comp.arch
Subject: Re: Why did Intel do it this way?
Message-ID: <4055@ima.ima.isc.com>
Date: 12 Jun 89 16:37:15 GMT
References: <19324@cup.portal.com>
Reply-To: johnl@ima.UUCP (John R. Levine)
Organization: Segue Software, Inc.
Lines: 26

In article <19324@cup.portal.com> ts@cup.portal.com (Tim W Smith) writes:
>On the 80286 in protected mode, a segment register contains 13 bits of
>segment number and ... 3 bits of other stuff [in] the least significant bits.
>
>If they had [put them in the high bits] then by setting up the GDT and LDT
>properly, one could have a linear address space.
>
>Someone suggested to me once that perhaps they used the three
>lower bits because ... they don't have to do any shifting to generate the
>byte offset into the [segment descriptor] table.

That doesn't make sense -- this is hardware, not software, and they can wire
the segment register to the descriptor address generator any way they want.
Besides, looking up a descriptor is still so slow that it's hard to believe
they would have been worried about that micro-optimization; they didn't even
check to see if the new descriptor value is the same as the old one.

I have two theories: A) They thought that being able to mask out the privilege
bits in the low bits would be somehow easier on the programmer, e.g. this way
you can compare two descriptors to see which is greater without doing any
masking. B) If they made it too easy to do 32-bit addressing, nobody would
want a 386.
-- 
John R. Levine, Segue Software, POB 349, Cambridge MA 02238, +1 617 492 3869
{ bbn | spdcc | decvax | harvard | yale }!ima!johnl, Levine@YALE.something
Massachusetts has 64 licensed drivers who are over 100 years old.  -The Globe