Path: utzoo!utgpu!jarvis.csri.toronto.edu!rutgers!apple!voder!pyramid!prls!philabs!jyc From: jyc@philabs.philips.com (Jonathan Yang Chen) Newsgroups: comp.lsi Subject: Re: EDIF Message-ID: <54260@philabs.Philips.Com> Date: 1 Jun 89 15:56:41 GMT Sender: news@philabs.Philips.Com Distribution: usa Organization: Philips Laboratories, Briarcliff Manor, NY Lines: 160 In article <1412@ncr-sd.SanDiego.NCR.COM> mildredm@babel.SanDiego.NCR.COM (Mildred Magboo) writes: >I am currently working on a translator that will >convert a netlist file into an EDIF format. I >need to know if there is anybody out there who >can provide me assistance in the conversion >process. >The only reference material I have is the EDIF 2 0 0 >Standard reference book. Please send me e-mail if you >know anything about EDIF, particularly 'netlist' >view. Mike Waters and other people already mentioned the resources and references for EDIF work. I just want to list an example of EDIF 2 0 0 netlist that may be of help. During the course of my work, I need translators between EDIF and the GDT's L database (GDT is a trademark of Silicon Compiler Systems (SCS) Corp. in New Jersey). Since SCS does not provide the translators, I started to write my own. Is anyone doing similar work? Maybe we can exchange informations. The following is an EDIF netlist of an CMOS opamp. We have a copy of University of Manchester's EDIF syntax checker; I used it for the syntax checking of this netlist. However, I cannot guarantee that the netlist is correct since I just started working on EDIF and no other people within Philips Laboratories are experienced and/or actively working on EDIF interface. If anyone find any errors or want to make a suggestion, please send me an Email. ------------------------------------------------------------------------ (EDIF (Rename design "opamp.e") (EdifVersion 2 0 0) (EdifLevel 0) (KeywordMap (KeywordLevel 0)) (Status (Written (TimeStamp 1989 5 24 15 35 0) (Program "LtoEDIF" (Version "V200")) (Author "Jonathan Y. Chen"))) (Design opamp (CellRef opamp (LibraryRef L_1))) (Library (Rename L_0 "/gdt/bin/Led") (EDIFLevel 0) (Technology (NumberDefinition (Scale 1 (E 1 3)(Unit Resistance)) (Scale 1 (E 1 -12)(Unit Capacitance)))) (Comment "The following cells are devices") (Cell TN (CellType GENERIC) (View V (ViewType NETLIST) (Interface (Port d) (Port s) (Port gr))) (Property SPICEPAR (String "W=4 L=3")) ) (Cell TP (CellType GENERIC) (View V (ViewType NETLIST) (Interface (Port d) (Port s) (Port gr))) (Property SPICEPAR (String "W=4 L=3")) ) (Cell capacitor (CellType GENERIC) (View V (ViewType NETLIST) (Interface (Port d (Direction INOUT)) (Port s (Direction INOUT)))) (Property SPICEPAR (String "5 pF")) ) (Cell resistor (CellType GENERIC) (View V (ViewType NETLIST) (Interface (Port d (Direction INOUT)) (Port s (Direction INOUT)))) (Property SPICEPAR (String "7 K")) ) ) (Library (Rename L_1 "/user/jyc/Ledif/test") (EDIFLevel 0) (Technology (NumberDefinition (Scale 1 (E 1 3)(Unit Resistance)) (Scale 1 (E 1 -12)(Unit Capacitance)))) (Comment "This is the netlist of an opamp") (Cell opamp (CellType GENERIC) (View V (ViewType NETLIST) (Interface (Port p0 (Designator "VDD")) (Port p1 (Designator "VDD")) (Joined (PortRef p0) (PortRef p1)) (Port p2 (Designator "GND")) (Port p3 (Designator "GND")) (Port p4 (Designator "GND")) (Joined (PortRef p2) (PortRef p3) (PortRef p4)) (Port p5 (Direction OUTPUT) (Designator "OUT")) (Port p6 (Direction INPUT) (Designator "IN")) (Port p7 (Direction INPUT) (Designator "IN")) (Port p8 (Direction INPUT) (Designator "IN")) ) (Contents (Instance t0 (ViewRef V (CellRef TP (LibraryRef L_0))) (Property SPICEPAR (String "W=60 L=8"))) (Instance t1 (ViewRef V (CellRef TP (LibraryRef L_0))) (Property SPICEPAR (String "W=150 L=5"))) (Instance t2 (ViewRef V (CellRef TP (LibraryRef L_0))) (Property SPICEPAR (String "W=150 L=5"))) (Instance t3 (ViewRef V (CellRef TN (LibraryRef L_0))) (Property SPICEPAR (String "W=45 L=10"))) (Instance t4 (ViewRef V (CellRef TN (LibraryRef L_0))) (Property SPICEPAR (String "W=45 L=10"))) (Instance t5 (ViewRef V (CellRef TP (LibraryRef L_0))) (Property SPICEPAR (String "W=120 L=8"))) (Instance t6 (ViewRef V (CellRef TN (LibraryRef L_0))) (Property SPICEPAR (String "W=90 L=10"))) (Instance i0 (ViewRef V (CellRef resistor (LibraryRef L_0)))) (Instance i1 (ViewRef V (CellRef capacitor (LibraryRef L_0)))) (Net N_0 (Joined (PortRef d (InstanceRef t1)) (PortRef s (InstanceRef t0)))) (Net N_1 (Joined (PortRef p0) (PortRef p1))) (Net N_2 (Joined (PortRef d (InstanceRef t0)) (PortRef p0))) (Net N_3 (Joined (PortRef d (InstanceRef t2)) (PortRef s (InstanceRef t0)))) (Net N_4 (Joined (PortRef s (InstanceRef t1)) (PortRef d (InstanceRef t3)))) ...... /* nets omitted to reduce the message length */ (Net N_20 (Joined (PortRef d (InstanceRef i0)) (PortRef s (InstanceRef i1)))) (Net N_21 (Joined (PortRef d (InstanceRef i1)) (PortRef d (InstanceRef t6)))) ) ) ) ) ) ------------------------------------------------------------------------ Jonathan Y. Chen Philips Laboratories Phone: (914) 945-6299 North American Philips Corporation Email: jyc@philabs.philips.com 345 Scarborough Road Fax: (914) 945-6375 Briarcliff Manor, NY 10510 Telex: 646326 philab bfrf