Path: utzoo!attcan!utgpu!utstat!jarvis.csri.toronto.edu!rutgers!sun-barr!oliveb!mipos3!mipos2.intel.com!sundar
From: sundar@mipos2.intel.com (Sundar Iyengar~)
Newsgroups: comp.lsi
Subject: Mixed mode simulation for chip design
Message-ID: <228@mipos3.intel.com>
Date: 8 Jun 89 15:40:51 GMT
Sender: news@mipos3.intel.com
Reply-To: sundar@mipos2.intel.com (Sundar Iyengar~)
Organization: Microprocessor Component Group, Intel Corp., Santa Clara, CA
Lines: 35


Has anybody tried applying mixed mode simulation techniques to chip design?
In a mixed mode model, different parts of the model would be at different
abstraction level.  Board designers certainly use such techniques.  I am not
a board designer, but let me describe what I think the usual design practice
is.  For a board design, typically one or more chips are still not
available, and hence bus functional models of the missing chips are used in
the simulation.  At this stage, only the bus logic is designed and debugged.
However, to examine performance trade-offs, the real chips or full
functional models are requir
ed so that the actual activity on the system bus
could be monitored.  Full functional models are either too time consuming to
work with or they are not available.  Hence, the designers usually end up
waiting for the real chips.  As one can see, there is a clear separation
between debug and performance tweak activities.

It seems to me that, in order to use mixed mode simulation techniques
at the chip level, the same separation has to be achieved.  However,
the chip designers usually do not separate debug from performance
tweaks.  In order to fully test a module, clock by clock description
of all activities at the module interface is necessary.  However,
if the design outside the module under test is at a more abstract
level, a full description of the interface activity may not be possible.
Given this, is mixed mode simulation viable for chip design?

Any comments?

Sundar Iyengar                      Microprocessor Design

UUCP:  intelca!mipos3!mipos2!sundar Intel, SC4-59
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Disclaimer:  The questions have been raised for reasons of cultural
             enrichment only.