Path: utzoo!utgpu!jarvis.csri.toronto.edu!rutgers!apple!oliveb!amdahl!sdg
From: sdg@uts.amdahl.com (Subrata Dasgupta)
Newsgroups: comp.lsi
Subject: Re: Mixed mode simulation for chip design
Message-ID: <98KK02mD33RK01@amdahl.uts.amdahl.com>
Date: 10 Jun 89 00:33:16 GMT
References: <228@mipos3.intel.com>
Reply-To: sdg@amdahl.uts.amdahl.com (Subrata Dasgupta)
Organization: Amdahl Corporation, Sunnyvale CA
Lines: 28

>Given this, is mixed mode simulation viable for chip design?
>
>Any comments?
>

Mixed mode simulation is definitely viable and has been tried in chip
design  at various organizations.  I don't see any reason why it would
be possible to apply mixed mode simulation to a board-level design and
not be feasible for chip design. Speaking from my own experience at
Duke University, we simulate VLSI chips using Leonardo (a mixed-mode
simulator). It is possible to do functional/behavioral, gate-level,
and circuit-level simulation using Leonardo.

A typical VLSI design cycle consists of simulation, design, and testing
iterated several times before a design becomes fabricated. It is in this
process that mixed-level simulation can be very useful. The typical stages
in the design process supported by Leonardo are: chip prototyping: -this
includes functional modeling and register-level design evaluation;
standard cell layout: -gate level simulation of the entire design,
followed by circuit level simulation. At every stage, the designer has the
option of replacing a section of the chip by it's corresponding high-level
model.

So, to answer the original question, yes, mixed-level design is not only
feasible for chip design it is more so than board-level design because of
the reduced requirements on memory resources over board-level design.

Subrata (sdg@uts.amdahl.com)