Path: utzoo!utgpu!jarvis.csri.toronto.edu!rutgers!apple!bloom-beacon!bu-cs!buengc!marco
From: marco@buengc.BU.EDU (Marco Zelada)
Newsgroups: comp.lsi
Subject: Re: Mixed mode simulation for chip design
Message-ID: <3102@buengc.BU.EDU>
Date: 10 Jun 89 16:11:37 GMT
References: <228@mipos3.intel.com> <98KK02mD33RK01@amdahl.uts.amdahl.com>
Reply-To: marco@buengc.bu.edu (Marco Zelada)
Followup-To: comp.lsi
Organization: Boston Univ. Col. of Eng.
Lines: 23

In article <98KK02mD33RK01@amdahl.uts.amdahl.com> sdg@amdahl.uts.amdahl.com (Subrata Dasgupta) writes:
>
>Mixed mode simulation is definitely viable and has been tried in chip
>design  at various organizations.  I don't see any reason why it would
>be possible to apply mixed mode simulation to a board-level design and
>not be feasible for chip design. Speaking from my own experience at
>Duke University, we simulate VLSI chips using Leonardo (a mixed-mode
>simulator). It is possible to do functional/behavioral, gate-level,
>and circuit-level simulation using Leonardo.

	Where could one get the Leonardo simulator you mention here ?
I would be very interested in trying it out on a project I am working
on right now.

	Thank you in advance.

-- 
___________________________________________________________________________
| Name:	 Marco Zelada                  | Tel: 617 353 9882, Fax: 353 6322 |	
| Group: VLSI CAD Research Laboratory  | E-mail: marco@buengc.bu.edu      |	
| Dept:  Electrical & Computer Eng.    | US-Mail: 44 Cummington St.       |
| Org:   Boston University             |	     Boston MA, 02215     |
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