Path: utzoo!utgpu!jarvis.csri.toronto.edu!rutgers!apple!amdahl!sdg From: sdg@uts.amdahl.com (Subrata Dasgupta) Newsgroups: comp.lsi Subject: Re: Mixed mode simulation for chip design Message-ID: Date: 10 Jun 89 17:37:33 GMT References: <228@mipos3.intel.com> <98KK02mD33RK01@amdahl.uts.amdahl.com> <3102@buengc.BU.EDU> Reply-To: sdg@amdahl.uts.amdahl.com (Subrata Dasgupta) Organization: Amdahl Corporation, Sunnyvale CA Lines: 28 In article <3102@buengc.BU.EDU> marco@buengc.bu.edu (Marco Zelada) writes: >In article <98KK02mD33RK01@amdahl.uts.amdahl.com> sdg@amdahl.uts.amdahl.com (Subrata Dasgupta) writes: >> >>Mixed mode simulation is definitely viable and has been tried in chip >>design at various organizations. I don't see any reason why it would >>be possible to apply mixed mode simulation to a board-level design and >>not be feasible for chip design. Speaking from my own experience at >>Duke University, we simulate VLSI chips using Leonardo (a mixed-mode >>simulator). It is possible to do functional/behavioral, gate-level, >>and circuit-level simulation using Leonardo. > > Where could one get the Leonardo simulator you mention here ? >I would be very interested in trying it out on a project I am working >on right now. The Leonardo simulator I used was being developed and wasn't released as a tool to organizations outside Duke. This was about 10 months back. One of the original goals of the project was to incorporate it as part of the OASIS (Open Architecture Silicon Implementation System) tools developed jointly at MCNC and Duke. I'm not sure if at this time it is available or not. But if it is, you can get more informayion by sending email to: Franz Brglz (MCNC) brglz@mcnc.org or Gershon Kedem at kedem@cs.duke.edu. You can also get more info. about the status of the Leonardo system from Jack Briner (jvb@cs.duke.edu) who was the principle person behind the project. Subrata Dasgupta